Careers

Location: Bengaluru, India

Company: QFocus India Pvt. Ltd. 

Domain: VLSI

Description

We are seeking an experienced ASIC Physical Design Engineer to join our team to work with one of the world’s leading technology organizations developing innovative AI and data center infrastructure solutions. The ideal candidate will be responsible for end-to-end physical implementation — from synthesis to GDSII— for large-scale, high-performance SoCs. This position offers opportunities to work on advanced technology nodes, collaborate with global design and verification teams and contribute to first-pass silicon success.

Key Responsibilities

• Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM and physical verification in advanced technology nodes.
• Resolve design and flow issues related to the physical design, identify potential solutions and drive execution.
• Deliver physical design of an end-to-end IP or integrate ASIC/SoC design and point out lower power and higher performance trade-offs.
• Define and implement schemes, including semi-custom placement and routing, to improve performance and power.
• Work with the RTL design team to understand partition architecture and drive physical aspects early in the design cycle.
• Interface with the RTL design team to drive design modifications that resolve congestion/timing issues, and implement functional ECOs.
• Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
• Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions.

Required Skills

• Strong hands-on experience in ASIC/SoC Physical Design implementation (netlist to GDSII).
• Proficiency in EDA tools such as Innovus, ICC2, Genus/DC, PrimeTime, Calibre, Redhawk/Voltus.
• Experience with advanced technology nodes (≤ 5 nm) and large-scale SoC designs.
• Strong expertise in timing analysis, power optimization, and physical verification.
• Scripting proficiency in TCL, Python or Shell within Unix/Linux environments.
• Excellent analytical, problem-solving and collaboration skills.

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or a related technical field, or equivalent practical experience.

Experience

Minimum 5+ years in ASIC/SoC Physical Design, with proven experience handling complex, high-performance silicon at advanced process nodes.

QFocus AI Pvt .Ltd. is an Equal Employment Opportunity employer.